1304 search results - page 65 / 261 » Evaluating Hardware Compilation Techniques |
173
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MICRO
1997
IEEE
15 years 8 months ago
1997
IEEE
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
123
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DATE
2004
IEEE
15 years 8 months ago
2004
IEEE
We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimizatio...
133
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ISCAS
2008
IEEE
15 years 10 months ago
2008
IEEE
C-based design techniques and methodologies have been proposed to tackle the complexity of heterogeneous embedded systems. The heterogeneity comes in the functionalities and the im...
130
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DATE
2000
IEEE
15 years 8 months ago
2000
IEEE
The widespread adoption of embedded microprocessor-based systems for safety critical applications mandates the use of co-design tools able to evaluate system dependability at ever...
146
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MICRO
2007
IEEE
15 years 10 months ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...