1304 search results - page 74 / 261 » Evaluating Hardware Compilation Techniques |
128
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ISLPED
2005
ACM
15 years 10 months ago
2005
ACM
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
104
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
A technique for evaluating noise figure suitable for BIST implementation is described. It is based on a low cost single-bit digitizer, which allows the simultaneous evaluation of ...
150
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DATE
2009
IEEE
15 years 8 months ago
2009
IEEE
Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic agains...
123
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ASPDAC
1999
ACM
15 years 8 months ago
1999
ACM
We describe a high performance clocking methodology for domino pipelines. Our technique maximizes the clock rate of the circular pipeline (“ring”) while maintaining the ring c...
124
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AICCSA
2006
IEEE
15 years 8 months ago
2006
IEEE
This paper proposes functional networks as an unconstrained classifier scheme for multivariate data to diagnose the breast cancer tumor. The performance of this new technique is m...