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» Evaluating Hardware Compilation Techniques
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ISLPED
2005
ACM
86views Hardware» more  ISLPED 2005»
15 years 10 months ago
An evaluation of code and data optimizations in the context of disk power reduction
Disk power management is becoming increasingly important in high-end server and cluster type of environments that execute dataintensive applications. While hardware-only approache...
Mahmut T. Kandemir, Seung Woo Son, Guangyu Chen
MST
2010
146views more  MST 2010»
14 years 11 months ago
The Cache-Oblivious Gaussian Elimination Paradigm: Theoretical Framework, Parallelization and Experimental Evaluation
We consider triply-nested loops of the type that occur in the standard Gaussian elimination algorithm, which we denote by GEP (or the Gaussian Elimination Paradigm). We present tw...
Rezaul Alam Chowdhury, Vijaya Ramachandran
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
16 years 1 months ago
Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation
Modeling and simulating pipelined processors in procedural languages such as C/C++ requires lots of cost in handling concurrent events, which hinders fast simulation. A number of ...
In-Cheol Park, Se-Hyeon Kang, Yongseok Yi
ECBS
2007
IEEE
122views Hardware» more  ECBS 2007»
15 years 10 months ago
Time- and Space-Efficient Evaluation of Sparse Boolean Functions in Embedded Software
The paper addresses software implementation of large sparse systems of Boolean functions. Fast evaluation of such functions with the smallest memory consumption is often required ...
Vaclav Dvorak
ISQED
2005
IEEE
92views Hardware» more  ISQED 2005»
15 years 10 months ago
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays
In this paper, design and measurement results of a test chip that intends to evaluate differences between layout techniques for rectangular unit-capacitor arrays are introduced. P...
DiaaEldin Khalil, Mohamed Dessouky, Vincent Bourgu...