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» Evaluating Hardware Compilation Techniques
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CPE
1997
Springer
104views Hardware» more  CPE 1997»
13 years 11 months ago
Measurement Tools and Modeling Techniques for Evaluating Web Server Performance
John Dilley, Rich Friedrich, Tai Jin, Jerome A. Ro...
ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
14 years 4 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid
IEEEPACT
2007
IEEE
14 years 2 months ago
A Loop Correlation Technique to Improve Performance Auditing
Performance auditing is an online optimization strategy that empirically measures the effectiveness of an optimization on a particular code region. It has the potential to greatly...
Jeremy Lau, Matthew Arnold, Michael Hind, Brad Cal...
ICS
2005
Tsinghua U.
14 years 1 months ago
Low-power, low-complexity instruction issue using compiler assistance
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S...
DAC
1999
ACM
14 years 8 months ago
Behavioral Synthesis Techniques for Intellectual Property Protection
? The economic viability of the reusable core-based design paradigm depends on the development of techniques for intellectual property protection. We introduce the first dynamic wa...
Inki Hong, Miodrag Potkonjak