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» Evaluating Hardware Compilation Techniques
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ISSS
2002
IEEE
124views Hardware» more  ISSS 2002»
15 years 9 months ago
A New Performance Evaluation Approach for System Level Design Space Exploration
Application specific systems have potential for customization of design with a view to achieve a better costperformance-power trade-off. Such customization requires extensive de...
M. Balakrishnan, Anshul Kumar, C. P. Joshi
ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
16 years 1 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...
ASPDAC
2000
ACM
95views Hardware» more  ASPDAC 2000»
15 years 8 months ago
Fair watermarking techniques
Many intellectual property protection (IPP) techniques have been proposed. Their primary objectives are providing convincible proof of authorship with least degradation of the qua...
Gang Qu, Jennifer L. Wong, Miodrag Potkonjak
SIGMETRICS
2008
ACM
128views Hardware» more  SIGMETRICS 2008»
15 years 4 months ago
Loss-aware network coding for unicast wireless sessions: design, implementation, and performance evaluation
Local network coding is growing in prominence as a technique to facilitate greater capacity utilization in multi-hop wireless networks. A specific objective of such local network ...
Shravan K. Rayanchu, Sayandeep Sen, Jianming Wu, S...
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
15 years 8 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah