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» Evaluating Run-Time Techniques for Leakage Power Reduction
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VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 8 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
FGCN
2008
IEEE
125views Communications» more  FGCN 2008»
14 years 2 months ago
Coordinating System Software for Power Savings
Power consumption is becoming a primary concern as a result of tremendous increasing in computer power usage. Innumerable methods and techniques have been exploited to address thi...
Lingxiang Xiang, Jiangwei Huang, Tianzhou Chen
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Adaptive techniques for overcoming performance degradation due to aging in digital circuits
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
CHES
2003
Springer
100views Cryptology» more  CHES 2003»
14 years 26 days ago
Multi-channel Attacks
We introduce multi-channel attacks, i.e., side-channel attacks which utilize multiple side-channels such as power and EM simultaneously. We propose an adversarial model which combi...
Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi
ICCAD
2009
IEEE
121views Hardware» more  ICCAD 2009»
13 years 5 months ago
MOLES: Malicious off-chip leakage enabled by side-channels
Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circui...
Lang Lin, Wayne Burleson, Christof Paar