201 search results - page 7 / 41 » Evaluating Run-Time Techniques for Leakage Power Reduction |
MICRO
2002
IEEE
13 years 7 months ago
2002
IEEE
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
With process scaling, leakage power reduction has become one of the most important design concerns. Multi-threshold techniques have been used to reduce runtime leakage power witho...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
— Run-time Active Leakage Reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the ...
VLSID
2008
IEEE
14 years 8 months ago
2008
IEEE
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Intege...