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» Evaluating coverage of error detection logic for soft errors...
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DATE
2000
IEEE
90views Hardware» more  DATE 2000»
15 years 8 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
128
Voted
ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
16 years 12 days ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
124
Voted
ESWS
2009
Springer
15 years 10 months ago
Ontology Integration Using Mappings: Towards Getting the Right Logical Consequences
Abstract. We propose a general method and novel algorithmic techniques to facilitate the integration of independently developed ontologies using mappings. Our method and techniques...
Ernesto Jiménez-Ruiz, Bernardo Cuenca Grau,...
CODES
2004
IEEE
15 years 7 months ago
System-on-chip validation using UML and CWL
In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design...
Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo...
117
Voted
PRDC
2008
IEEE
15 years 10 months ago
Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy
Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree ...
Viswanathan Subramanian, Arun K. Somani