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» Evaluating kilo-instruction multiprocessors
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DAMON
2007
Springer
14 years 1 months ago
Parallel buffers for chip multiprocessors
Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among ...
John Cieslewicz, Kenneth A. Ross, Ioannis Giannaka...
EUROPAR
2004
Springer
14 years 28 days ago
Modular On-chip Multiprocessor for Routing Applications
Abstract. Simulation platforms for network processing still have difficulties in finding a good compromise between speed and accuracy. This makes it difficult to identify the caus...
Saifeddine Berrayana, Etienne Faure, Daniela Geniu...
3DIC
2009
IEEE
169views Hardware» more  3DIC 2009»
14 years 20 days ago
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerase...
ICCD
2000
IEEE
69views Hardware» more  ICCD 2000»
13 years 12 months ago
Hierarchical Simulation of a Multiprocessor Architecture
When proposing new architectural enhancements, it is also important to account for the hardware complexity. To achieve this goal, we propose to model the new design in a hardware ...
Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
13 years 11 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg