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» Evaluating kilo-instruction multiprocessors
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ISPASS
2009
IEEE
14 years 2 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
HPCA
2009
IEEE
14 years 8 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
ASPLOS
2010
ACM
14 years 2 months ago
SherLog: error diagnosis by connecting clues from run-time logs
Computer systems often fail due to many factors such as software bugs or administrator errors. Diagnosing such production run failures is an important but challenging task since i...
Ding Yuan, Haohui Mai, Weiwei Xiong, Lin Tan, Yuan...
CODES
2007
IEEE
14 years 1 months ago
Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems
In battery-powered embedded systems, dedicated circuitry is used to convert stored energy into a form that can be directly used by processors. These power regulation devices seek ...
Seunghoon Kim, Robert P. Dick, Russ Joseph
ISCA
2007
IEEE
149views Hardware» more  ISCA 2007»
14 years 1 months ago
Virtual private caches
Virtual Private Machines (VPM) provide a framework for Quality of Service (QoS) in CMP-based computer systems. VPMs incorporate microarchitecture mechanisms that allow shares of h...
Kyle J. Nesbit, James Laudon, James E. Smith