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DAC
2003
ACM
14 years 8 months ago
Instruction encoding synthesis for architecture exploration using hierarchical processor models
This paper presents a novel instruction encoding generation technique for use in architecture exploration for application specific processors. The underlying exploration methodolo...
Achim Nohl, Volker Greive, Gunnar Braun, Andreas H...
DAC
2005
ACM
13 years 9 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
ASPDAC
2007
ACM
123views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Creating Explicit Communication in SoC Models Using Interactive Re-Coding
Communication exploration has become a critical step during SoC design. Researchers in the CAD community have proposed fast and efficient techniques for comprehensive design space ...
Pramod Chandraiah, Junyu Peng, Rainer Dömer
RTCSA
2007
IEEE
14 years 1 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
DAC
1999
ACM
13 years 11 months ago
ipChinook: an Integrated IP-based Design Framework for Distributed Embedded Systems
IPCHINOOK is a design tool for distributed embedded systems. It gains leverage from the use of a carefully chosen set of design ions that raise the level of designer interaction d...
Pai H. Chou, Ross B. Ortega, Ken Hines, Kurt Partr...