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PATMOS
2005
Springer
14 years 3 months ago
Power - Performance Optimization for Custom Digital Circuits
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
Radu Zlatanovici, Borivoje Nikolic
DDECS
2007
IEEE
106views Hardware» more  DDECS 2007»
14 years 4 months ago
A Proposal for ASM++ Diagrams
– Algorithmic State Machines are a 40-year old tool for the design of digital circuits. They are a good alternative to Finite State Machines, where only states can be properly de...
Santiago De Pablo, Santiago Cáceres, Jes&ua...
ICCAD
2002
IEEE
154views Hardware» more  ICCAD 2002»
14 years 6 months ago
Concurrent flip-flop and repeater insertion for high performance integrated circuits
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
Pasquale Cocchini
DAC
2005
ACM
14 years 10 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
IJRR
2007
117views more  IJRR 2007»
13 years 9 months ago
Wave Haptics: Building Stiff Controllers from the Natural Motor Dynamics
— Haptics, like the fields of robotics and motion control, relies on high stiffness position control of electric motors. Traditionally DC motors are driven by current amplifier...
Nicola Diolaiti, Günter Niemeyer, Neal A. Tan...