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HPCA
2011
IEEE
12 years 11 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...
DATE
2002
IEEE
137views Hardware» more  DATE 2002»
14 years 1 months ago
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
Qin Zhao, Bart Mesman, Twan Basten
IWMM
2010
Springer
125views Hardware» more  IWMM 2010»
13 years 10 months ago
Efficient memory shadowing for 64-bit architectures
Shadow memory is used by dynamic program analysis tools to store metadata for tracking properties of application memory. The efficiency of mapping between application memory and s...
Qin Zhao, Derek Bruening, Saman P. Amarasinghe
ETS
2006
IEEE
119views Hardware» more  ETS 2006»
14 years 2 months ago
On-Chip Test Generation Using Linear Subspaces
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
Ramashis Das, Igor L. Markov, John P. Hayes
ICCBR
2005
Springer
14 years 1 months ago
Learning to Win: Case-Based Plan Selection in a Real-Time Strategy Game
While several researchers have applied case-based reasoning techniques to games, only Ponsen and Spronck (2004) have addressed the challenging problem of learning to win real-time ...
David W. Aha, Matthew Molineaux, Marc J. V. Ponsen