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ICCAD
1996
IEEE
121views Hardware» more  ICCAD 1996»
14 years 7 days ago
Identification of unsettable flip-flops for partial scan and faster ATPG
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
ASPDAC
2007
ACM
99views Hardware» more  ASPDAC 2007»
14 years 2 days ago
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm
Abstract - This paper presents a fast and accurate global routing algorithm, DpRouter, based on two efficient techniques: (1) dynamic pattern routing (Dpr), and (2) segment movemen...
Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, ...
DSD
2006
IEEE
99views Hardware» more  DSD 2006»
13 years 11 months ago
Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads
We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis m...
Rikard Thid, Ingo Sander, Axel Jantsch
JSA
2010
173views more  JSA 2010»
13 years 2 months ago
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
Quentin L. Meunier, Frédéric P&eacut...
SIGCOMM
1994
ACM
14 years 4 days ago
Experiences with a High-Speed Network Adaptor: A Software Perspective
This paper describes our experiences, from a software perspective, with the OSIRIS network adaptor. It first identifies the problems we encountered while programming OSIRIS and op...
Peter Druschel, Larry L. Peterson, Bruce S. Davie