122 search results - page 22 / 25 » Evolvable Hardware for the Generation of Sequential Filter C... |
VLSID
2001
IEEE
14 years 7 months ago
2001
IEEE
Networking hardware manufacturers face the dual demands of supporting ever increasing bandwidth requirements, while also delivering new features, such as the ability to implement ...
ITC
2000
IEEE
13 years 11 months ago
2000
IEEE
An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstructi...
DSD
2005
IEEE
13 years 8 months ago
2005
IEEE
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
DATE
2005
IEEE
14 years 9 days ago
2005
IEEE
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...