Sciweavers

307 search results - page 53 / 62
» Exception Handling: An Architecture Model and Utility Suppor...
Sort
View
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 1 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
MICRO
2007
IEEE
168views Hardware» more  MICRO 2007»
14 years 1 months ago
Global Multi-Threaded Instruction Scheduling
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
Guilherme Ottoni, David I. August
CODES
2005
IEEE
14 years 1 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
IPPS
2008
IEEE
14 years 1 months ago
Wait-free Programming for General Purpose Computations on Graphics Processors
The fact that graphics processors (GPUs) are today’s most powerful computational hardware for the dollar has motivated researchers to utilize the ubiquitous and powerful GPUs fo...
Phuong Hoai Ha, Philippas Tsigas, Otto J. Anshus
MM
1997
ACM
97views Multimedia» more  MM 1997»
13 years 11 months ago
A Failure and Overload Tolerance Mechanism for Continuous Media Servers
–Large scale clustered continuous media (CM) servers deployed in applications like video-on-demand have high availability requirements. In the event of server failure, streams fr...
Rajesh Krishnan, Dinesh Venkatesh, Thomas D. C. Li...