3893 search results - page 7 / 779 » Execution Architectures and Compilation |
ISCA
2008
IEEE
14 years 3 months ago
2008
IEEE
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in t...
LCPC
2001
Springer
14 years 1 months ago
2001
Springer
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
ICPPW
2005
IEEE
14 years 2 months ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
ASPLOS
1989
ACM
14 years 1 months ago
1989
ACM
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...