453 search results - page 22 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Utilizing on-chip caches in embedded multiprocessorsystem-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work th...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
RTAS
2005
IEEE
14 years 1 months ago
2005
IEEE
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
ACSD
2003
IEEE
14 years 28 days ago
2003
IEEE
This paper presents a synthesis approach for reactive systems that aims at minimizing the overhead introduced by the operating system and the interaction among the concurrent task...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adop...