453 search results - page 27 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
HPCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machin...
ISCA
2010
IEEE
14 years 14 days ago
2010
IEEE
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
MSE
2002
IEEE
14 years 17 days ago
2002
IEEE
This paper presents the study of running several core multimedia applications on a simultaneous multithreading (SMT) architecture and derives design principles for multimedia soft...