453 search results - page 39 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
HPCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
IPPS
1998
IEEE
14 years 1 months ago
1998
IEEE
This work deals with the scheduling problem of a directed acyclic graph with interprocessor communication delays. The objective is to minimize the makespan, taking into account the...
ESTIMEDIA
2004
Springer
14 years 2 months ago
2004
Springer
Abstract— This paper presents an exploration framework which performs data assignment and access scheduling exploration for applications given a multilayer memory architecture. O...
SIGOPS
2010
13 years 3 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
IEEEPACT
2005
IEEE
14 years 2 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...