453 search results - page 47 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
DATE
2010
IEEE
14 years 2 months ago
2010
IEEE
—This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value...
CODES
2003
IEEE
14 years 2 months ago
2003
IEEE
NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and ...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access will result in a definite cache hit or miss. This unpredictabilit...
ISCA
2003
IEEE
14 years 2 months ago
2003
IEEE
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...