453 search results - page 7 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
HIPEAC
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. On multi-core architectures with software-managed memories, effectively orchestrating data movement is essential to performance, but is tedious and error-prone. In this p...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
IEEEINTERACT
2003
IEEE
14 years 25 days ago
2003
IEEE
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
ASAP
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digi...