453 search results - page 82 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
ICCD
1999
IEEE
13 years 12 months ago
1999
IEEE
Current trends in DRAM memory chip fabrication have led many researchers to propose \intelligent memory" architectures that integrate microprocessors or logic with memory. Su...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
In the design of real-time and embedded systems, it is important to establish a bound on the worst-case execution time (WCET) of programs to assure via schedulability analysis tha...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
ICDCS
2010
IEEE
13 years 11 months ago
2010
IEEE
— As network infrastructures with 10 Gb/s bandwidth and beyond have become pervasive and as cost advantages of large commodity-machine clusters continue to increase, research and...