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» Execution levels for aspect-oriented programming
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ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
13 years 9 days ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
ASPLOS
2012
ACM
12 years 4 months ago
Understanding modern device drivers
Device drivers are the single largest contributor to operating-system kernel code with over 5 million lines of code in the Linux kernel, and cause significant complexity, bugs an...
Asim Kadav, Michael M. Swift
PPOPP
2010
ACM
14 years 3 months ago
Load balancing on speed
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
Steven Hofmeyr, Costin Iancu, Filip Blagojevic
AOSD
2009
ACM
14 years 3 months ago
Modelling hardware verification concerns specified in the e language: an experience report
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...
Darren Galpin, Cormac Driver, Siobhán Clark...
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
14 years 3 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel