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» Experiences in Hardware Trojan Design and Implementation
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MICRO
2008
IEEE
116views Hardware» more  MICRO 2008»
14 years 1 months ago
Power reduction of CMP communication networks via RF-interconnects
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...
M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyu...
ICCAD
1997
IEEE
108views Hardware» more  ICCAD 1997»
13 years 11 months ago
Negative thinking by incremental problem solving: application to unate covering
We introduce a new technique to solve exactly a discrete optimization problem, based on the paradigm of “negative” thinking. The motivation is that when searching the space of...
Evguenii I. Goldberg, Luca P. Carloni, Tiziano Vil...
ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
14 years 2 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
CARDIS
2000
Springer
107views Hardware» more  CARDIS 2000»
13 years 12 months ago
JCCap: Capability-based Access Control for Java Card
: This paper describes JCCap, a protection facility for cooperating applications in the context of Java Card. It enables the control of access rights between mutually suspicious ap...
Daniel Hagimont, Jean-Jacques Vandewalle
CAV
2006
Springer
95views Hardware» more  CAV 2006»
13 years 11 months ago
Yasm: A Software Model-Checker for Verification and Refutation
Example Guided Abstraction Refinement (CEGAR) [6] framework. A number of wellengineered software model-checkers are available, e.g., SLAM [1] and BLAST [12]. Why build another one?...
Arie Gurfinkel, Ou Wei, Marsha Chechik