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» Experiences with Soft-Core Processor Design
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MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
14 years 2 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
DEBU
2008
136views more  DEBU 2008»
13 years 8 months ago
Towards a Unified Declarative and Imperative XQuery Processor
Since the birth of XML, the processing of XML query languages like XQuery/XQueryP has been widely researched in the academic and industrial communities. Most of the approaches con...
Zhen Hua Liu, Anguel Novoselsky, Vikas Arora
DAC
2011
ACM
12 years 7 months ago
Throughput maximization for periodic real-time systems under the maximal temperature constraint
We study the problem on how to maximize the throughput for a periodic real-time system under the given peak temperature constraint. We assume that different tasks in our system ma...
Huang Huang, Gang Quan, Jeffrey Fan, Meikang Qiu
CISIS
2010
IEEE
14 years 2 months ago
Threaded Dynamic Memory Management in Many-Core Processors
—Current trends in desktop processor design have been toward many-core solutions with increased parallelism. As the number of supported threads grows in these processors, it may ...
Edward C. Herrmann, Philip A. Wilsey
ANCS
2006
ACM
13 years 11 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo