352 search results - page 26 / 71 » Experiences with Soft-Core Processor Design |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we present an approach to the design optimization of faulttolerant embedded systems for safety-critical applications. Processes are statically scheduled and communic...
MSE
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short co...
EUROPAR
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. Current approaches to parallel I/O demand extensive user effort to obtain acceptable performance. This is in part due to difficulties in understanding the characteristics...
FPL
2007
Springer
14 years 2 months ago
2007
Springer
In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, avail...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...