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SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
14 years 3 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
HICSS
1994
IEEE
118views Biometrics» more  HICSS 1994»
14 years 1 months ago
A Distributed Architecture for an Instructable Problem Solver
Our research goal is to design systems that enable humans to teach tedious, repetitive, simple tasks to a computer. We propose here a learner/problem solver architecture for such ...
Jacky Baltes, Bruce A. MacDonald
DAC
2002
ACM
14 years 10 months ago
An integer linear programming based approach for parallelizing applications in On-chip multiprocessors
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneous...
Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 2 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
TC
2011
13 years 4 months ago
Energy Reduction in Consolidated Servers through Memory-Aware Virtual Machine Scheduling
—Increasing energy consumption in server consolidation environments leads to high maintenance costs for data centers. Main memory, no less than processor, is a major energy consu...
Jae-Wan Jang, Myeongjae Jeon, Hyo-Sil Kim, Heeseun...