375 search results - page 20 / 75 » Explicit gate delay model for timing evaluation |
ISPD
1997
ACM
13 years 12 months ago
1997
ACM
In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations a...
CDC
2009
IEEE
13 years 11 months ago
2009
IEEE
The paper is devoted to the stability analysis of linear time varying delay. We first model the time varying delay system as an interconnected system between a known linear trans...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
BC
1999
13 years 7 months ago
1999
A model is presented to study and quantify the contribution of all available sensory information to human standing based on optimal estimation theory. In the model, delayed sensory...