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ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Cycle error correction in asynchronous clock modeling for cycle-based simulation
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
Junghee Lee, Joonhwan Yi
DAC
1994
ACM
13 years 11 months ago
A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules
Current asynchronous tools are focussed mainly on the design of a single interface module. In many applications, one must design interacting interface modules that potentially comm...
Gjalt G. de Jong, Bill Lin
CHES
2006
Springer
146views Cryptology» more  CHES 2006»
13 years 10 months ago
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits
This paper presents a Path Swapping (PS) method which enables to enhance the security of Quasi Delay Insensitive Asynchronous Circuits against Power Analysis (PA) attack. This appr...
G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
ARCS
2006
Springer
13 years 10 months ago
Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors
Abstract. This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results usin...
Nabil Hasasneh, Ian Bell, Chris R. Jesshope
JSA
2007
152views more  JSA 2007»
13 years 6 months ago
Asynchronous arbiter for micro-threaded chip multiprocessors
This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. T...
Nabil Hasasneh, Ian Bell, Chris R. Jesshope