290 search results - page 57 / 58 » Exploiting Temporal Uncertainty in Parallel and Distributed ... |
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
IEEEPACT
2003
IEEE
14 years 23 days ago
2003
IEEE
This paper presents a framework for analyzing the performance of multithreaded programs using a model called a constraint graph. We review previous constraint graph definitions fo...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
Improvements in semiconductor technology now enable Chip Multiprocessors (CMPs). As many future computer systems will use one or more CMPs and support shared memory, such systems ...
NETCOOP
2009
Springer
14 years 2 months ago
2009
Springer
The fundamental limits on channel capacity form a barrier to the sustained growth on the use of wireless networks. To cope with this, multi-path communication solutions provide a p...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
Hardware transactional memory should support unbounded transactions: transactions of arbitrary size and duration. We describe a hardware implementation of unbounded transactional ...