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» Exploiting Vector Parallelism in Software Pipelined Loops
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CASES
2007
ACM
13 years 11 months ago
Non-transparent debugging for software-pipelined loops
This paper tackles the problem of providing correct information about program variable values in a software-pipelined loop through a non-transparent debugging approach. Since mode...
Hugo Venturini, Frédéric Riss, Jean-...
ISHPC
2000
Springer
13 years 11 months ago
Loop Termination Prediction
Deeply pipelined high performance processors require highly accurate branch prediction to drive their instruction fetch. However there remains a class of events which are not easi...
Timothy Sherwood, Brad Calder
ISCA
2000
IEEE
78views Hardware» more  ISCA 2000»
13 years 11 months ago
Vector instruction set support for conditional operations
Vector instruction sets are receiving renewed interest because of their applicability to multimedia. Current multimedia instruction sets use short vectors with SIMD implementation...
James E. Smith, Greg Faanes, Rabin A. Sugumar
CODES
2005
IEEE
14 years 1 months ago
Iterational retiming: maximize iteration-level parallelism for nested loops
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean ...
MICRO
1991
IEEE
115views Hardware» more  MICRO 1991»
13 years 11 months ago
Executing Loops on a Fine-Grained MIMD Architecture
- We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processor...
Sunah Lee, Rajiv Gupta