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TCAD
2008
127views more  TCAD 2008»
13 years 7 months ago
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozor...
ICMCS
2006
IEEE
113views Multimedia» more  ICMCS 2006»
14 years 1 months ago
On Parallelization of a Video Mining System
As digital video data becomes more pervasive, mining information from multimedia data becomes increasingly important. Although researches in multimedia mining area have shown grea...
Wenlong Li, Eric Li, Nan Di, Carole Dulong, Tao Wa...
HOTI
2005
IEEE
14 years 1 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
ICCAD
2008
IEEE
162views Hardware» more  ICCAD 2008»
14 years 4 months ago
MAPS: multi-algorithm parallel circuit simulation
— The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing paral...
Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif
ISCA
2003
IEEE
123views Hardware» more  ISCA 2003»
14 years 19 days ago
Detecting Global Stride Locality in Value Streams
Value prediction exploits localities in value streams. Previous research focused on exploiting two types of value localities, computational and context-based, in the local value h...
Huiyang Zhou, Jill Flanagan, Thomas M. Conte