41 search results - page 3 / 9 » Exploiting program cyclic behavior to reduce memory latency ... |
126
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HPCA
2006
IEEE
16 years 4 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
157
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CASES
2003
ACM
15 years 9 months ago
2003
ACM
Bank locality can be defined as localizing the number of load/store accesses to a small set of memory banks at a given time. An optimizing compiler can modify a given input code t...
176
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ECRTS
2007
IEEE
15 years 10 months ago
2007
IEEE
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by...
145
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EUROPAR
2009
Springer
15 years 8 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
121
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ASPDAC
2004
ACM
15 years 9 months ago
2004
ACM
The design of future high-performance embedded systems is hampered by two problems: First, the required hardware needs more energy than is available from batteries. Second, curren...