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» Exploiting regularity for low-power design
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DATE
2008
IEEE
97views Hardware» more  DATE 2008»
13 years 11 months ago
Energy Efficient and High Speed On-Chip Ternary Bus
We propose two crosstalk reducing coding schemes using ternary busses. In addition to low power consumption and reduced delay, our schemes offer other advantages over binary codin...
Chunjie Duan, Sunil P. Khatri
RAID
2009
Springer
14 years 4 months ago
Regular Expression Matching on Graphics Hardware for Intrusion Detection
The expressive power of regular expressions has been often exploited in network intrusion detection systems, virus scanners, and spam filtering applications. However, the flexibl...
Giorgos Vasiliadis, Michalis Polychronakis, Spyros...
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
14 years 4 months ago
An adaptable FPGA-based System for Regular Expression Matching
In many applications string pattern matching is one of the most intensive tasks in terms of computation time and memory accesses. Network Intrusion Detection Systems and DNA Seque...
Ivano Bonesana, Marco Paolieri, Marco D. Santambro...
CASES
2003
ACM
14 years 3 months ago
Power efficient encoding techniques for off-chip data buses
Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...
VTS
2005
IEEE
95views Hardware» more  VTS 2005»
14 years 3 months ago
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
Baosheng Wang, Yuejian Wu, Josh Yang, André...