59 search results - page 6 / 12 » Exploring Memory Hierarchy with ArchC |
DATE
2003
IEEE
14 years 23 days ago
2003
IEEE
This paper details the first step of the Design Trotter framework for design space exploration applied to dedicated SOCs. The aim of this step is to provide metrics in order to gu...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
ICS
1999
Tsinghua U.
13 years 11 months ago
1999
Tsinghua U.
Programming languages that provide multidimensional arrays and a flat linear model of memory must implement a mapping between these two domains to order array elements in memory....
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
ASPLOS
2006
ACM
13 years 11 months ago
2006
ACM
Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size desig...