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» Exploring Performance Tradeoffs for Clustered VLIW ASIPs
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ISSS
2000
IEEE
109views Hardware» more  ISSS 2000»
14 years 2 days ago
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors
The paper presents a novel software-pipelining algorithm suitable for optimizing compilers targeting embedded VLIW processors. The proposed algorithm is different from previous ap...
Cagdas Akturan, Margarida F. Jacome
DATE
2002
IEEE
137views Hardware» more  DATE 2002»
14 years 1 months ago
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
Qin Zhao, Bart Mesman, Twan Basten
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
14 years 23 days ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
DATE
2009
IEEE
139views Hardware» more  DATE 2009»
14 years 3 months ago
Cross-architectural design space exploration tool for reconfigurable processors
—Processors that deploy fine-grained reconfigurable fabrics to implement application-specific accelerators ondemand obtained significant attention within the last decade. They tr...
Lars Bauer, Muhammad Shafique, Jörg Henkel
PDP
2006
IEEE
14 years 2 months ago
A Distributed Query Structure to Explore Random Mappings in Parallel
We explore the possibilities to organize a query data structure in the main memories or hard disks of a cluster computer. The query data structure serves to improve the performanc...
Jan Heichler, Jorg Keller