33 search results - page 5 / 7 » Exploring Wakeup-Free Instruction Scheduling |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Application-specific customization of the instruction set helps embedded processors achieve significant performance and power efficiency. In this paper, we explore customizatio...
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
ASPLOS
2006
ACM
14 years 2 months ago
2006
ACM
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
HPCA
1997
IEEE
14 years 19 days ago
1997
IEEE
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...