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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
14 years 3 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
14 years 3 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
CODES
2006
IEEE
14 years 3 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
PDC
2004
ACM
14 years 2 months ago
On the spot experiments within healthcare
This paper reports the value of On the Spot Experiments with self-produced content and the use of technology within healthcare. On the Spot Experiments are experiments conducted i...
Erling Björgvinsson, Per-Anders Hillgren
VISSYM
2007
13 years 11 months ago
A Tri-Space Visualization Interface for Analyzing Time-Varying Multivariate Volume Data
The dataset generated by a large-scale numerical simulation may include thousands of timesteps and hundreds of variables describing different aspects of the modeled physical pheno...
Hiroshi Akiba, Kwan-Liu Ma