62 search results - page 11 / 13 » Extended resolution simulates binary decision diagrams |
DAC
2010
ACM
13 years 11 months ago
2010
ACM
State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems: (1) ...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...
VLSID
1999
IEEE
13 years 12 months ago
1999
IEEE
In this paper we address the problem of detailed FPGA routing using Boolean formulation methods. In the context of FPGA routing where routing resources are fixed, Boolean formulat...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— In many verification tools methods for functional simulation based on reduced ordered Binary Decision Diagrams (BDDs) are used. The evaluation time for a BDD can be crucial an...