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» Extending Platform-Based Design to Network on Chip Systems
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FPL
2007
Springer
126views Hardware» more  FPL 2007»
14 years 1 months ago
A Time-Triggered Network-on-Chip
In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature...
Martin Schoeberl
ASAP
2003
IEEE
108views Hardware» more  ASAP 2003»
14 years 1 months ago
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
Terry Tao Ye, Giovanni De Micheli
ISCAS
2005
IEEE
146views Hardware» more  ISCAS 2005»
14 years 1 months ago
A novel approach for network on chip emulation
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
ASPDAC
2009
ACM
135views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Analysis of communication delay bounds for network on chips
—In network-on-chip, computing worst-case delay bound for packet delivery is crucial for designing predictable systems but yet an intractable problem due to complicated resource ...
Yue Qian, Zhonghai Lu, Wenhua Dou
DATE
2006
IEEE
100views Hardware» more  DATE 2006»
14 years 1 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer