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» Extending Platform-Based Design to Network on Chip Systems
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SLIP
2006
ACM
14 years 1 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
DAC
1999
ACM
14 years 3 days ago
On-Chip Inductance Issues in Multiconductor Systems
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
Shannon V. Morton
ICCAD
2004
IEEE
64views Hardware» more  ICCAD 2004»
14 years 4 months ago
Simultaneous design and placement of multiplexed chemical processing systems on microchips
Microchip structures represent an attractive platform for microscale chemical processing of fluidic systems. However, standardized design methods for these devices have not yet b...
Anton J. Pfeiffer, Tamal Mukherjee, Steinar Hauan
JSA
2010
158views more  JSA 2010»
13 years 2 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
14 years 2 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh