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ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 6 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
DAC
1996
ACM
14 years 1 months ago
Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems
-- This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us ...
Eric Verlind, Gjalt G. de Jong, Bill Lin
WSC
1997
13 years 10 months ago
Business Process Modeling with SIMPROCESS
This paper gives an overview of business process modeling with SIMPROCESS, its applications, unique features, basic and advanced modeling constructs, and benefits. 1 WHAT IS SIMPR...
Scott Swegles
ARESEC
2011
145views more  ARESEC 2011»
12 years 9 months ago
An Attribute Based Framework for Risk-Adaptive Access Control Models
—The concept of risk-based adaptive access control (RAdAC, pronounced Raid-ack) has been recently introduced in the literature. It seeks to automatically (or semi-automatically) ...
Savith Kandala, Ravi S. Sandhu, Venkata Bhamidipat...
MICRO
2010
IEEE
119views Hardware» more  MICRO 2010»
13 years 7 months ago
A Predictive Model for Dynamic Microarchitectural Adaptivity Control
Abstract--Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resou...
Christophe Dubach, Timothy M. Jones, Edwin V. Boni...