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ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang
ISLPED
2004
ACM
151views Hardware» more  ISLPED 2004»
14 years 1 months ago
Dynamic voltage and frequency scaling based on workload decomposition
This paper presents a technique called “workload decomposition” in which the CPU workload is decomposed in two parts: on-chip and off-chip. The on-chip workload signifies the ...
Kihwan Choi, Ramakrishna Soma, Massoud Pedram
PVLDB
2010
112views more  PVLDB 2010»
13 years 6 months ago
Two-way Replacement Selection
The performance of external sorting using merge sort is highly dependent on the length of the runs generated. One of the most commonly used run generation strategies is Replacemen...
Xavier Martinez-Palau, David Dominguez-Sal, Josep-...
TPDS
2008
101views more  TPDS 2008»
13 years 7 months ago
An Energy-Oriented Evaluation of Buffer Cache Algorithms Using Parallel I/O Workloads
Power consumption is an important issue for cluster supercomputers as it directly affects running cost and cooling requirements. This paper investigates the memory energy efficienc...
Jianhui Yue, Yifeng Zhu, Zhao Cai
DAC
2006
ACM
14 years 8 months ago
A parallelized way to provide data encryption and integrity checking on a processor-memory bus
This paper describes a novel engine, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), enabling to guarantee confidentiality and integrity of data exchanged b...
Reouven Elbaz, Lionel Torres, Gilles Sassatelli, P...