Sciweavers

276 search results - page 4 / 56
» Extremely Low-Power Logic
Sort
View
ICCAD
1994
IEEE
73views Hardware» more  ICCAD 1994»
13 years 11 months ago
Low power state assignment targeting two-and multi-level logic implementations
Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvi...
IWANN
2005
Springer
14 years 1 months ago
Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures
Abstract. In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low pow...
Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
14 years 1 months ago
A low power merge cell processor for real-time spike sorting in implantable neural prostheses
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
M. D. Linderman, T. H. Meng
VTC
2006
IEEE
134views Communications» more  VTC 2006»
14 years 1 months ago
Ultra Low-Power Digital Demodulators for Short Range Applications
— In this paper we present extremely flexible and low power digital binary ASK, PSK, and FSK demodulator architectures for short-range applications that uses limiter amplifier (i...
Mehmet R. Yuce, Ahmet Tekin