5 search results - page 1 / 1 » FACTOR: A Hierarchical Methodology for Functional Test Gener... |
DATE
2002
IEEE
14 years 11 days ago
2002
IEEE
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
Higher levels of integration, the need for test re-use, and the mixed-signal nature of today’s SOC’s necessitate hierarchical test generation and system level test composition...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
BIODATAMINING
2008
13 years 7 months ago
2008
Background: Analysis of a microarray experiment often results in a list of hundreds of diseaseassociated genes. In order to suggest common biological processes and functions for t...