27 search results - page 4 / 6 » FDRA: A Software-Pipelining Algorithm for Embedded VLIW Proc... |
ICCD
1999
IEEE
13 years 12 months ago
1999
IEEE
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
CASES
2004
ACM
14 years 1 months ago
2004
ACM
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...