42 search results - page 3 / 9 » FPGA global routing architecture optimization using a multic... |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
DAGSTUHL
2006
13 years 9 months ago
2006
This paper presents a method of constructing pre-routed FPGA cores which lays the foundations for a rapid system construction framework for dynamically reconfigurable computing sy...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
We propose a novel optimization scheme that can improve the routing by reducing a newly observed router decaying effect. A pair of greedy-grow algorithms, each emphasizing a diffe...
ICCAD
1993
IEEE
13 years 11 months ago
1993
IEEE
In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an ex...