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» FPGA interconnect design using logical effort
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RSP
1999
IEEE
122views Control Systems» more  RSP 1999»
13 years 11 months ago
Incremental Compilation for Logic Emulation
Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic...
Russell Tessier
FPGA
1995
ACM
142views FPGA» more  FPGA 1995»
13 years 11 months ago
The Design of RPM: An FPGA-based Multiprocessor Emulator
Recent advances in Field-Programmable Gate Arrays (FPGA) and programmable interconnects have made it possible to build efficient hardware emulation engines. In addition, improveme...
Koray Öner, Luiz André Barroso, Sasan ...
ASPDAC
2005
ACM
149views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Leakage control in FPGA routing fabric
Abstract— As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unus...
Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykr...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 4 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
14 years 1 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...