363 search results - page 35 / 73 » FPGA interconnect design using logical effort |
124
Voted
ICASSP
2008
IEEE
15 years 10 months ago
2008
IEEE
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
108
Voted
IPPS
2006
IEEE
15 years 9 months ago
2006
IEEE
Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices...
153
Voted
RSP
2008
IEEE
15 years 10 months ago
2008
IEEE
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
132
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DAC
2006
ACM
16 years 4 months ago
2006
ACM
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
118
Voted
MICRO
2002
IEEE
15 years 8 months ago
2002
IEEE
With the prevalence of server blades and systems-ona-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limite...